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ltc3646/ltc3646-1 1 36461f typical a pplica t ion fea t ures descrip t ion 40v, 1a synchronous step-down converter the lt c ? 3646 is a high efficiency, step-down dc/dc converter with internal high side and synchronous power fets. it draws only 140 a typical dc supply current in burst mode operation at no load while maintaining output voltage regulation. the ltc3646 can supply up to a 1 a load, and its combina- tion of burst mode operation, integrated power switches and low quiescent current provides high efficiency over a broad range of load currents. alternatively, it can be used in forced continuous mode for ripple sensitive applications . the ltc3646 has a wide 4.0 v to 40 v input range and its patented controlled on- time architecture and 0.6 v reference voltage allow for large step-down ratios without the risk of overvoltage. the frequency may be set between 200khz to 3.0 mhz with a program resistor or synchronized to an external clock. the internal soft-start, short-circuit protection and volt- age rating make the ltc3646 a robust part ideal for high voltage applications. efficiency curve a pplica t ions n wide input voltage range: 4.0v to 40v n 1a guaranteed output current n high efficiency: up to 95% n wide output voltage range ltc3646: 2.0v to 30v ltc3646-1: 0.6v to 15v n 1% accurate reference voltage n internal or external compensation n switching frequency adjustable and synchronizable: 200khz to 3mhz n selectable high efficiency burst mode ? operation or forced continuous mode n 14 lead 3mm 4mm dfn or thermally enhanced 16-lead msop packages n point of load power supply n intermediate bus power n automotive applications l, lt , lt c , lt m , linear technology, the linear logo and burst mode are registered trademarks and hot swap is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents, including 6580258, 5481178, 5994885, 6304066, 5847554, 6476589, 6774611. load current (a) 0.001 efficiency (%) power loss (w) 40 60 1 3646 ta01b 20 0 0.1 0.01 100 30 50 10 70 80 90 0.4 0.2 0.8 0 1.0 0.6 v out = 3.3v v out = 5v v out = 3.3v v out = 5v v in = 12v f = 1mhz pvin svin run intv cc mode/sync ith rt extv cc boost sw v on v fb + ? switch control ltc3646 3.3h sgnd 4.7f pgnd 0.1f 412k 10f 0.6v 56.2k 3646 ta01a 15f v out 5v 1a v in 40v max
ltc3646/ltc3646-1 2 36461f a bsolu t e maxi m u m r a t ings pvin , svin supply voltage ........................ C0. 3 v to 45 v sw voltage ( dc ) ........................... C 0.3 v to pvin + 0.3 v boost C sw voltage ................................... C 0.3 v to 6v v on voltage ................................................ C 0.3 v to 33 v mode / sync , rt, ith , v fb voltage ................................ C 0.3 v to intv cc + 0.3 v intv cc voltage ............................................ C 0.3 v to 6v (notes 1, 7) 1 2 3 4 5 6 7 14 13 12 11 10 9 8 svin run extv cc intv cc boost sw pvin sgnd v fb ith rt v on pgood mode/sync top view 15 pgnd de package 14-lead (4mm 3mm) plastic dfn t jmax = 150c, ja = 43c/w exposed pad (pin 15) is pgnd, must be soldered to pcb 1 2 3 4 5 6 7 8 sgnd v fb ith rt v on pgood mode/sync nc 16 15 14 13 12 11 10 9 svin run extv cc intv cc boost sw pvin pvin top view 17 pgnd mse package 16-lead plastic msop t jmax = 150c, ja = 38c/w exposed pad (pin 17) is pgnd, must be soldered to pcb p in c on f igura t ion o r d er i n f or m a t ion lead free finish tape and reel part marking package description temperature range ltc3646ede#pbf ltc3646ede#trpbf 3646 14-lead (4mm 3mm) plastic dfn C40c to 85c ltc3646ide#pbf ltc3646ide#trpbf 3646 14-lead (4mm 3mm) plastic dfn C40c to 125c ltc3646hde#pbf ltc3646hde#trpbf 3646 14-lead (4mm 3mm) plastic dfn C40c to 150c ltc3646emse#pbf ltc3646emse#trpbf 3646 16-lead plastic msop C40c to 85c ltc3646imse#pbf ltc3646imse#trpbf 3646 16-lead plastic msop C40c to 125c ltc3646hmse#pbf ltc3646hmse#trpbf 3646 16-lead plastic msop C40c to 150c ltc3646ede-1#pbf ltc3646ede-1#trpbf 36461 14-lead (4mm 3mm) plastic dfn C40c to 85c ltc3646ide-1#pbf ltc3646ide-1#trpbf 36461 14-lead (4mm 3mm) plastic dfn C40c to 125c ltc3646hde-1#pbf ltc3646hde-1#trpbf 36461 14-lead (4mm 3mm) plastic dfn C40c to 150c ltc3646emse-1#pbf ltc3646emse-1#trpbf 36461 16-lead plastic msop C40c to 85c ltc3646imse-1#pbf ltc3646imse-1#trpbf 36461 16-lead plastic msop C40c to 125c ltc3646hmse-1#pbf ltc3646hmse-1#trpbf 36461 16-lead plastic msop C40c to 150c consult lt c marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. for more information on lead free part marking, go to: http:// www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ extv cc voltage ........................................... C 0.3 v to 6v run voltage ............................................... C0.3 v to 45 v pgood ....................................... C 0.3 v to intv cc + 0.3 v operating junction temperature range ( note 2) .................................................. C 40 c to 150 c storage temperature range .................. C 65 c to 150 c lead temperature ( soldering , 10 sec ) mse .......... 30 0 c
ltc3646/ltc3646-1 3 36461f e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c (note 2), pvin = svin = 12v unless otherwise noted. symbol parameter conditions min typ max units input supply (pvin, svin) v in input voltage operating range l 4.0 40 v v in(ov) input supply overvoltage lockout v in rising hysteresis (v in falling) l l 43.5 2.0 46 2.5 2.9 v v v in(uv) input supply undervoltage lockout v in falling hysteresis (v in rising) 3.2 3.35 250 3.5 v mv i q dc supply current (note 3) forced continuous sleep mode shutdown mode v run = 0v 620 140 8 875 190 a a a main control loop v out output voltage range (note 4) ltc3646 ltc3646-1 2.0 0.6 30 15 v v v fb feedback reference voltage C40c < t a < 85c l 0.594 0.591 0.6 0.6 0.606 0.609 v v feedback v oltage line regulation v in = 4.0v to 40v, i th = 1.5v 0.05 % feedback v oltage load regulation i th = 1.0v to 1.8v 0.12 % feedback input current v fb = 0.6v l 0 20 na g m(ea) error amplifier transconductance external comp 300 s t on(min) minimum on-time v in = 40v, r rt = 30k, v on = 2v 30 ns t off(min) minimum off-time 80 ns i lim valley switch current limit l 0.9 1.2 1.5 a internal oscillator frequency v rt = v intvcc r rt = 450k r rt = 60k r rt = 30k 1.6 0.19 1.25 2.55 2.25 0.2 1.5 3.0 2.95 0.27 1.75 3.45 mhz mhz mhz mhz external clock frequency range 0.2 3.0 mhz r ds(on) top switch on-resistance (note 5) bottom switch on-resistance (note 5) v in = 5.5v v in = 5.5v 200 120 m? m? switch leakage v in = v sw = 40v, v run = 0 v in = 40v, v sw = 0v, v run = 0 1 1 a a internal v cc regulator v intvcc intv cc voltage l 4.8 5.0 5.2 v intv cc load regulation (note 6) i intvcc = 0ma to 5ma 0.5 % intv cc undervoltage lockout intv cc falling 3.0 v intv cc uvlo hysteresis 0.3 v extv cc switchover voltage extv cc rising 4.25 4.5 4.65 v extv cc hysteresis 200 mv operation v run run pin threshold run rising run falling hysteresis 1.17 1.06 1.21 1.10 110 1.26 1.14 v v mv run pin leakage current run = 1.3v 0 1 a v pgood(ut) pgood overvoltage threshold fb rising fb falling 5.0 3.5 7.5 5 10 %v fb v pgood(lt ) pgood undervoltage threshold fb falling fb rising C5.0 C3.5 C7.5 C5 C10 %v fb t pgood pgood filter time rt = intv cc 15 30 s
ltc3646/ltc3646-1 4 36461f e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c (note 2), pvin = svin = 12v unless otherwise noted. symbol parameter conditions min typ max units r pgood pgood pull-down resistance i pgood = 10ma 63 ? pgood leakage v pgood = v intvcc 1.0 a t ss internal soft-start time 250 500 s v mode/sync mode threshold voltage sync threshold voltage mode v ih mode v il sync ih sync il l l l l 1.2 1.2 0.3 0.3 v v v v mode/sync input current 1 2 a internal ith voltage threshold l intv cc C 0.3v v v on pin input impedance ltc3646 ltc3646-1 520 600 k k note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the ltc3646 is tested under pulsed load conditions such that t j t a . the ltc3646e is guaranteed to meet specifications from 0c to 85c junction temperature. specifications over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the ltc3646i is guaranteed over the C40c to 125c operating junction temperature range and the ltc3646h is guaranteed over the C40c to 150c operating junction temperature range. high junction temperatures derate operating lifetimes; operating lifetime is derated for junction temperatures greater than 125c. note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. note 3: dynamic supply current is higher due to gate charging being delivered at the switch frequency. note 4: limits to v out are a subject to pvin, svin, t on ( min ) , t off ( min ) , and frequency constraints. see the applications information section for a further discussion. these items are tested with appropriate combinations of v in , v on and frequency. note 5: r ds(on) is guaranteed by correlation to wafer level measurements. note 6: maximum allowed current draw when used as a regulated output is 5ma. this supply is only intended to provide additional dc load current as needed and not to regulate large transient or ac behavior as such waveforms may impact ltc3646 operation. note 7: this ic includes overtemperature protection intended to protect the device during momentary overload conditions. the maximum junction temperature may be exceeded when overtemperature protection is active. continuous operation above the specified maximum operating junction temperature may result in device degradation or failure.
ltc3646/ltc3646-1 5 36461f typical p er f or m ance c harac t eris t ics efficiency vs input voltage, burst mode operation reference voltage vs temperature r ds(on) vs temperature switch pin leakage vs temperature and supply oscillator internal set frequency vs temperature efficiency vs load current, burst mode operation efficiency vs load current, forced continuous mode operation efficiency vs load current t a = 25c, svin/pvin = 12v, f o = 1mhz unless otherwise noted. oscillator externally set frequency vs temperature input voltage (v) 0 efficiency (%) 80 90 40 36461 g04 70 60 105 100 75 85 65 95 15 20 25 30 35 load = 500ma load = 100ma load = 1a l = 6.8h v out = 3.3v temperature (c) ?50 resistance () 0.20 0.30 150130110 36461 g06 0.10 0 ?10?30 0.35 0.15 0.25 0.05 10 30 50 70 90 main switch synchronous switch temperature (c) ?50 sw leakage current (a) 14 18 150130110 36461 g07 10 0 ?10?30 20 12 16 8 4 6 2 10 30 50 70 90 v ds = 12v, main switch v ds = 12v, synchronous switch v ds = 40v, main switch v ds = 40v, synchronous switch temperature (c) ?40 frequency (mhz) 2.35 2.45 140120100 36461 g08 2.25 2.00 0?20 2.50 2.30 2.40 2.20 2.10 2.15 2.05 20 40 60 80 v rt = v intvcc temperature (c) ?40 frequency (mhz) 1.5 1.7 140120100 36461 g09 1.3 1.2 0?20 1.8 1.4 1.6 20 40 60 80 r rt = 60k temperature (c) ?50 v ref (v) 600 604 150130110 36461 g05 596 592 ?10?30 608 598 602 594 606 10 30 50 70 90 load current (a) 0.001 efficiency (%) 40 60 1 36461 g01 20 0 0.1 0.01 100 30 50 10 70 80 90 v in = 5v v in = 8v v in = 12v v out = 1.8v f o = 1.5mhz load current (a) 0.001 efficiency (%) 40 60 1 36461 g02 20 0 0.1 0.01 100 30 50 10 70 80 90 v in = 5v v in = 8v v in = 12v v out = 1.8v f o = 1.5mhz load current (a) 0.001 efficiency (%) 40 60 1 36461 g03 20 0 0.1 0.01 100 30 50 10 70 80 90 forced continuous operation v out = 5v v out = 3.3v burst mode operation
ltc3646/ltc3646-1 6 36461f typical p er f or m ance c harac t eris t ics output voltage vs time, burst mode operation start-up from shutdown, burst mode operation start-up from shutdown, forced continuous mode load step, burst mode operation load step, forced continuous operation i q shutdown vs supply and temperature t a = 25c, svin/pvin = 12v, f o = 1mhz unless otherwise noted. bottom switch current limit vs temperature no load quiescent current vs temperature, burst mode operation load regulation temperature (c) ?40 no load quiescent current (a) 140 180 140120100 36461 g10 100 0?20 200 120 160 20 40 60 80 temperature (c) ?40 bottom switch current limit (a) 1.2 1.4 140120100 36461 g11 1.0 0?20 1.5 1.1 1.3 20 40 60 80 load current (a) 0 ?v out /v out (%) 0.8 1 36461 g12 ?0.4 0.2 0.4 0.6 1.6 0 0.4 0.8 1.2 v out = 5v forced continuous burst mode operation v in = 12v v out = 5v i load = 20ma 2s/div 36461 g13 v out 20mv/div ac-coupled i l 250ma/div sw 10v/div i load = 25ma 100s/div 36461 g14 v out 5v/div i l 250ma/div run 5v/div i load = 25ma 100s/div 36461 g15 v out 5v/div i l 250ma/div run 5v/div v out = 1.2v 50ma to 1a step f o = 2.25mhz r comp = 200k c comp = 33pf c f = 10pf c out = 15f 40s/div 36461 g16 v out ac-coupled 100mv/div i l 1a/div i load 1a/div v out = 1.2v 50ma to 1a step f o = 2.25mhz r comp = 200k c comp = 33pf c f = 10pf c out = 15f 10s/div 36461 g17 v out ac-coupled 100mv/div i l 1a/div i load 1a/div temperature (c) ?40 shutdown current (a) 80 120 140 100 36461 g18 0 ?20 200 40 60 60 10 20 30 40 50 v in = 40v v in = 12v
ltc3646/ltc3646-1 7 36461f p in func t ions (dfn/msop) sgnd (pin 1/pin 1): analog ground pin. this pin should have a low noise connection to the reference ground. v fb (pin 2/pin 2): output voltage feedback pin. input to the error amplifier that compares the feedback voltage with the internal 0.6 v reference. connect this pin to a resistor divider network to program the desired output voltage. ith (pin 3/pin 3): error amplifier output and switching regulator compensation point. connect this pin to appro- priate external components to compensate the regulator loop frequency response. connect this pin to intv cc to use the default internal compensation. rt (pin 4/pin 4): oscillator frequency program pin. con- nect an external resistor between 450 k and 30 k from this pin to sgnd to program the switching frequency from 200khz to 3.0 mhz. when rt is connected to intv cc , the switching frequency will be 2.25mhz. do not float rt . v on (pin 5/pin 5): on-time voltage input pin. this pin provides information about the output voltage (v out ) to the on-time control loop. connect this pin to the regulated output to make the on-time proportional to the output voltage. pgood (pin 6/pin 6): power good output pin. pgood is pulled to ground when the voltage at the v fb pin is not within 7.5% ( typical) of the internal 0.6 v reference. pgood becomes high impedance once the voltage at the v fb pin returns to within 5% of the internal reference. mode/sync (pin 7/pin 7): mode selection and external clock input pin. this pin forces the ltc3646 into forced continuous operation when tied to ground, and high ef- ficiency burst mode operation when tied to intv cc . when driven with an external clock, the ltc3646 will adjust the top switch on-time to match the switching frequency to the applied clock frequency and the part will operate in forced continuous mode. during start-up or external clock synchronization, the operating mode will be as described in the applications information section. pvin ( pin 8/pins 9, 10): supply pin for the power switch. this pin connects directly to top switch. closely decouple this pin to pgnd with a 10 f or greater, low esr capacitor. sw (pin 9/pin 11): switch node output pin. connect this pin to the switch side of the external inductor and boost capacitor. boost (pin 10/pin 12): boosted supply pin. a boosted voltage is generated at this pin by connecting a capacitor between this pin and the sw pin. the normal operation voltage swing of this pin ranges from intv cc to pvin + intv cc . when necessary, connect the cathode of an external boost diode to this pin. see the boost capacitor and diode section. intv cc (pin 11/pin 13): internal 5.0 v regulator output pin. this pin should be decoupled to pgnd with a 4.7 f or greater low esr capacitor. when necessary, connect the anode of an external boost diode to this pin. the internal regulator is disabled when the run pin is low. extv cc (pin 12/pin 14): use this input pin to power the chips low voltage control circuitry if a high efficiency supply between 4.5 v and 6.0 v is available. otherwise, connect this pin to sgnd. see the applications informa- tion section for further information. run (pin 13/pin 15): regulator enable pin. enables chip operation by applying a voltage greater than v run . svin (pin 14/pin 16): power supply input for internal circuitry. closely decouple this pin to sgnd with a greater than 1 f low esr capacitor. svin pin voltage should equal pvin in order to correctly calculate on the on time and maintain constant frequency operation. pgnd ( exposed pad pin 15/ exposed pad pin 17): power path ground pin . the exposed pad must be well soldered to the pcb to provide a low impedance electrical connec- tion to ground and rated thermal performance.
ltc3646/ltc3646-1 8 36461f func t ional b lock diagra m 3646 bd on-time controller oscillator control logic + ? + ? + ? + ? intv cc ? 0.3v + ? soft-start 0.6v ref ea uv ov r s q 5v reg 4.5v c svin 1.21v run mode/sync rt tg on bg v on r rt r comp c comp ith + ? c pvin pvin extv cc c vcc intv cc boost sw c boost v out c out svin + ? + ? 0.555v sense + sense ? 0.645v l1 pgnd pgood v fb sgnd i rev i cmp r1 r2 t on = v on v in ? f o
ltc3646/ltc3646-1 9 36461f o pera t ion the ltc3646 and ltc3646-1 are current mode, monolithic , synchronous, step-down regulators capable of 40 v input operation, and extremely high step down ratios while main- taining constant frequency . ( both will be referred to as the ltc3646 except as specifically noted.) part operation is enabled by raising the voltage of the run pin above 1.21 v. main control loop in normal operation a switching cycle is initiated by a signal from the inductor valley current comparator (i cmp in the block diagram). the top power mosfet is turned on, and a timer is simultaneously started in the on-time controller. the on-time controller computes the correct on time ( subject to t o n ( min ) ) based on the desired switching frequency f o , and step- down ratio v on /v in , according to the formula shown in the block diagram. in a typical applica- tion, the v on pin should be connected to the output voltage, v out . when the timer expires, the top power mosfet is turned off and the bottom power mosfet is turned on until the current comparator (i cmp ) trips, restarting the timer and initiating the next cycle. the inductor current is monitored by sensing the voltage drop across the sw and pgnd nodes of the bottom power mosfet. the volt- age at the ith node sets the i cmp comparator threshold corresponding to the inductor valley current . the error amplifier ( ea) adjusts the ith voltage by comparing an internal 0.6 v reference voltage to the feedback signal, v fb , derived from the output voltage. if, for example, the load current increases, the output voltage will decrease relative to the 0.6 v reference. the ith voltage will rise until the average inductor current increases to match the load current. at low load currents, the inductor current can drop to zero or become negative. if the ltc3646 is configured for burst mode operation, this inductor current condition is detected by the current reversal comparator (i rev ) which then shuts off the bottom power mosfet and places the part into a low quiescent current sleep state, resulting in discontinuous operation and increased efficiency at low load currents. both power mosfets will remain off with the part in sleep and the output capacitor supplying the load current until the ith voltage rises sufficiently to initiate another cycle. discontinuous operation is disabled by tying the mode/sync pin to ground, placing the ltc3646 into forced continuous mode. during forced continuous mode operation, synchronous operation occurs regardless of the output load current, and the inductor current trough levels are allowed to become negative. the operating frequency is determined by the value of the r rt resistor, which programs the current for the internal oscillator. an internal phase - locked loop adjusts the switch - ing regulator on-time so that the switching frequency matches the programmed frequency, subject to t on and t off time constraints shown in the electrical characteristics table. alternatively, the rt pin can be connected to the intv cc pin which causes the internal oscillator to run at the default frequency of 2.25mhz. a clock signal can be applied to the mode/sync pin to synchronize the switching frequency to an external source . when operating in this configuration, connect a resistor to the rt pin with a value corresponding to the applied clock frequency. with an external clock supplied to the mode/ sync pin, the part will operate in forced continuous mode. power good status output the pgood open-drain output will be pulled low if the regulator output exits the v pgood window around the regulation point. this condition is released once regula- tion within the specified window is achieved . to prevent unwanted pgood glitches during transients or dynamic v out changes, the ltc3646 pgood falling edge includes a filter time of approximately 70 clock cycles.
ltc3646/ltc3646-1 10 36461f o pera t ion svin/pvin overvoltage protection in order to protect the internal power mosfet devices against transient voltage spikes, the ltc3646 continuously monitors the svin pin for an overvoltage condition. when svin rises above v in(ov) , the regulator suspends opera- tion by shutting off both power mosfets and resetting the soft-start level. once v in drops to below the specified range of v in( ov) , the regulator immediately restarts normal operation. short-circuit protection the ltc3646 is designed to withstand output short circuits . in this situation the part will source i lim ( approximately 1.2a) plus half the inductor current ripple. since v out is at or near 0 v, the on-time will shorten and the off-time will lengthen considerably, resulting in a lower switching frequency.
ltc3646/ltc3646-1 11 36461f a general ltc3646 application circuit is shown on the first page of this data sheet. external component selection is largely driven by the load requirement and begins with the selection of the inductor l. once the inductor is chosen, the input capacitor, c in , the output capacitor, c out , the internal regulator capacitor, c vcc , and the boost capaci- tor, c boost , can be selected. next, the feedback resistors are selected to set the desired output voltage. finally, the remaining optional external components can be selected for functions such as external loop compensation, externally programmed oscillator frequency and pgood. operating frequency selection of the operating frequency is a trade-off between efficiency and component size. high frequency operation allows the use of smaller inductor and capacitor values. operation at lower frequencies improves efficiency by reducing internal gate charge losses but requires larger inductance values and/or capacitance to maintain low output ripple voltage. the operating frequency, f o , of the ltc3646 is determined by an external resistor that is con- nected between the rt pin and ground. the value of the resistor sets the ramp current that is used to charge and discharge an internal timing capacitor within the oscillator and can be calculated by using the following equation: r rt = 9e 10 f o where r rt is in and f o is in hz. a pplica t ions i n f or m a t ion connecting the rt pin to intv cc will assert the internal default f o = 2.25 mhz; however, this switching frequency will be more sensitive to process and temperature variations than using a resistor on rt ( see the typical performance characteristics section). inductor selection for a given input and output voltage, the inductor value and operating frequency determine the inductor ripple current. more specifically, the inductor ripple current decreases with higher inductor value or higher operating frequency according to the following equation: i l = v out f o ? l ? ? ? ? ? ? 1 ? v out v in ? ? ? ? ? ? where i l = inductor ripple current ( a), f o = operating frequency ( hz) and l = inductor value ( h). a trade-off be- tween component size, efficiency and operating frequency can be seen from this equation. accepting larger values of i l allows the use of lower value inductors but results in greater core loss in the inductor, greater esr loss in the output capacitor, and larger output ripple. generally, the highest efficiency operation is obtained at low operating frequency with small ripple current. the inductor value should be chosen to give a peak-to- peak ripple current of between 30% and 40% of i out(max) , where i out(max) equals the maximum average output current. note that the largest ripple current occurs at the highest v in . to guarantee the ripple current does not exceed a specified maximum, the inductance should be chosen according to: l = v out f o ? i l ? ? ? ? ? ? 1 ? v out v in ? ? ? ? ? ? once the value for l is known, the type of inductor must be selected. actual core loss is independent of core size for a fixed inductor value, but is very dependent on the inductance selected. as the inductance increases, core loss decreases. unfortunately, increased inductance requires more turns of wire leading to increased copper loss. figure 1 r rt (k) frequency (khz) 3000 1500 1000 2500 2000 500 0 400 200 300 100 3646 f01 500 0
ltc3646/ltc3646-1 12 36461f ferrite designs exhibit very low core loss and are preferred at high switching frequencies, so design goals can con- centrate on copper loss and preventing saturation. ferrite core materials saturate hard, meaning the inductance collapses abruptly when the peak design current is exceeded. this collapse will result in an abrupt increase in inductor ripple current, so it is important to ensure the core will not saturate. different core materials and shapes will change the size/ current and price/current relationship of an inductor. toroidal or shielded pot cores in ferrite or permalloy materials are small and dont radiate much energy but generally cost more than powdered iron core inductors with similar characteristics. the choice of which style inductor to use mainly depends on the price versus size requirements and any radiated field/emi requirements. new designs for surface mount inductors are available from toko, vishay, nec/tokin, cooper, coilcraft, tdk and wrth electronik. table 1 gives a sampling of available surface mount inductors. table 1. inductor selection inductance (h) dcr (m) max current (a) dimensions (mm) height (mm) wrth elektronik, tpc mh, l, lh series 3.3 (mh) 3.9 (l) 6.2 (lh) 35 55 45 1.8 2.1 1.7 4.8 4.8 5.8 5.8 5.8 5.8 2.8 1.8 2.8 sumida, cdrh3d23/hp series 1.2 3.3 40 70 3.5 2.2 3.92 3.92 3.92 3.92 2.5 2.5 tdk, slf10145 series 22 33 59 82 2.1 1.6 10.1 10.1 10.1 10.1 4.5 4.5 coilcraft mss7341 series 10 15 32 47 1.64 1.36 7.3 7.3 7.3 7.3 4.1 4.1 c in and c out selection the input capacitance, c in , is needed to filter the trapezoi- dal wave current at the drain of the top power mosfet. to prevent large voltage transients from occurring a low a pplica t ions i n f or m a t ion esr input capacitor sized for the maximum rms current is recommended. the maximum rms current is given by: i rms = i out(max) v out v in ? v out ( ) v in this formula has a maximum at v in = 2v out , where i rms = i out /2. this simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. note that ripple current ratings from capacitor manufacturers are often based on only 2000 hours of life which makes it advisable to further derate the capacitor or choose a capacitor rated at a higher temperature than required. several capacitors may be paralleled to meet the require- ments of the design. for low input voltage applications sufficient bulk input capacitance is needed to minimize transient effects during output load changes. even though the ltc3646 design includes an overvoltage protection circuit, care must always be taken to ensure input voltage transients do not pose an overvoltage hazard to the part. the selection of c out is primarily determined by the effec- tive series resistance ( esr) that is required to minimize voltage ripple and load step transients. the output ripple, v out , is determined by: v out < i l esr + 1 8 ? f o ? c out ? ? ? ? ? ? when using low-esr ceramic capacitors, it is more useful to choose the output capacitor value to fulfill a charge stor- age requirement. during a load step, the output capacitor must instantaneously supply the current to support the load until the feedback loop raises the switch current enough to support the load. the time required for the feedback loop to respond is dependent on the compensation and the output capacitor size. typically , 3 to 4 cycles are required to respond to a load step, but only in the first cycle does the output drop linearly. the output droop, v droop , is usually about 3 times the linear drop of the first cycle.
ltc3646/ltc3646-1 13 36461f a pplica t ions i n f or m a t ion thus, a good place to start is with the output capacitor size of approximately: c out 3 ? i out f o ? v droop though this equation provides a good approximation, more capacitance may be required depending on the duty cycle and load step requirements. the actual v droop should be verified by applying a load step to the output. using ceramic input and output capacitors higher value, lower cost ceramic capacitors are now available in small case sizes. their high voltage rating and low esr make them ideal for switching regulator ap- plications. however, due to the self-resonant and high-q characteristics of some types of ceramic capacitors, care must be taken when these capacitors are used at the input and output. when a ceramic capacitor is used at the input, and the power is supplied by a wall adapter through long wires, a load step at the output can induce ringing at the v in input. at best, this ringing can couple to the output and be mistaken as loop instability. at worst, a sudden inrush of current through the long wires can potentially cause a voltage spike at v in large enough to damage the part. for a more detailed discussion, refer to application note 88. when choosing the input and output ceramic capacitors choose the x5r or x7r dielectric formulations. these dielectrics provide the best temperature and voltage characteristics for a given value and size. intv cc regulator and extv cc an internal low dropout ( ldo) regulator produces a 5v supply voltage used to power much of the internal ltc3646 circuitry including the power mosfet gate drivers. the intv cc pin connects to the output of this regulator and should have 4.7 f of decoupling capacitance to ground. the decoupling capacitor should have low impedance electrical connections to the intv cc and pgnd pins to provide the transient currents required by the ltc3646. the user may draw a maximum load current of 5 ma from this pin but must take into account the increased power dissipation and die temperature that results. furthermore, this supply is intended only to supply additional dc load currents as desired; it is not intended to regulate large transient or ac behavior as this may impact ltc3646 operation. alternatively, if a suitable supply is available or can be generated, the power required to operate the low voltage circuitry of the ltc3646 can be supplied through the extv cc pin. when the voltage on the extv cc pin is be- low 4.5 v, the chip power is supplied by the internal ldo. as shown in the block diagram, when extv cc is above 4.5v, the internal ldo is shut off, and an internal switch is closed between the extv cc and intv cc pins. connect extv cc to sgnd if an external supply meeting these con- straints is not available.if the voltage on the extv cc pin is efficiently generated, this will result in the highest overall system efficiency and the least amount of heat generated by the ltc3646. this effectively decreased the no-load quiescent current by a factor of v out /v in . this topic is further discussed in the thermal considerations section. boost capacitor and diode the boost capacitor, c boost , is used to create a voltage rail above the applied input voltage v in . specifically, the boost capacitor is charged to a voltage equal to approximately intv cc each time the bottom power mosfet is turned on. the charge on this capacitor is then used to supply the required transient current during the remainder of the switching cycle. when the top mosfet is turned on, the boost pin voltage will be equal to approximately v in + intv cc . for most applications a 0.1 f ceramic capacitor will provide adequate performance. an internal switch is used to charge the boost capacitor when the synchronous mosfet is turned on. an external schottky diode can be connected between boost and intv cc in parallel with this switch in order to improve the capacitor refresh. for best performance and sufficient design margin an external diode must be used in circuits where v out is programmed to be above 12 v or the ic operates at a die temperature above 85 c. forward cur- rents through this diode are small, on the order of 10ma to 20 ma, but the diode chosen must have low reverse leakage current at the expected voltage and temperature.
ltc3646/ltc3646-1 14 36461f figure 2. optional feedforward capacitor v fb r1 r2 c f 3646 f02 v out sgnd ltc3646 a pplica t ions i n f or m a t ion the design example on the back page uses a dfls1200 based on its low reverse leakage over the voltage and temperature ratings of the ltc3646. output voltage programming the ltc3646 will adjust the output voltage such that v fb equals the reference voltage of 0.6v according to: v out = 0.6v 1 + r1 r2 ? ? ? ? ? ? the desired output voltage is set by the appropriate selec- tion of resistors r1 and r2 as shown in figure 2. choosing large values for r 1 and r 2 will result in improved efficiency but may lead to undesired noise coupling or phase margin reduction due to stray capacitance at the v fb node. care should be taken to route the fb line away from any noise source, such as the sw line. when programming output voltages above 12 v , a schottky diode connected between boost and intv cc is needed (see the boost capacitor and diode section.) to improve the frequency response of the main control loop a feedforward capacitor, c f , may be used as shown in figure 2. minimum off-time/on-time considerations the minimum off-time is the smallest amount of time that the ltc3646 can turn on the bottom power mosfet, trip the current comparator and turn off the power mosfet. this time is typically 80 ns. for the controlled on-time current mode control architecture, the minimum off-time limit imposes a maximum duty cycle of: dc (max) = 1 C (f o ? t off(min) ) where f o is the switching frequency and t off(min) is the minimum off - time. if the maximum duty cycle is surpassed, due to a dropping input voltage for example, the output will drop out of regulation. the minimum input voltage to avoid this dropout condition is: v in(min) = v out 1 ? f o ? t off(min) ( ) if there is concern about operating near the minimum off-time limits, consider reducing the frequency to add margin to the design. conversely, the minimum on-time is the smallest dura- tion of time in which the top power mosfet can be in its on state. this time is typically 30 ns. in continuous mode operation, the minimum on-time limit imposes a minimum duty cycle of: dc (min) = (f o ? t on(min) ) where t on(min) is the minimum on-time. as the equation shows, reducing the operating frequency will alleviate the minimum duty cycle constraint. in the rare cases where the minimum duty cycle is surpassed, the output voltage will still remain in regulation, but the switching frequency will decrease from its programmed value. this is an acceptable result in many applications, so this constraint may not be of critical importance in some cases, and high switching frequencies may be used in the design without any fear of severe consequences. as the sections on inductor and capacitor selection show, high switching frequencies allow the use of smaller board components, thus reducing the footprint of the application circuit.
ltc3646/ltc3646-1 15 36461f minimum on-time can be affected by the output load cur- rent and the trough current level. during the transition between the top switch turn-off and the synchronous switch turn-on, the inductor current discharges the sw pin capacitance. when the inductor trough current level is low, or reversing in forced continuous operation, the minimum on-time can increase by approximately 20ns. output voltage limits the block diagram shows that a sample of the output voltage ( taken through the v on pin) is used to servo the correct on-time for a given application duty cycle and frequency. this circuit limits the range of v out over which the ltc3646 will be able to adjust the on-time in order to match the selected frequency at a given duty cycle. the valid output range for the ltc3646 is 2.0 v to 30 v. for output voltage below 2.0 v, use the ltc3646-1 which has a valid output range of between 0.6v and 15v. it is important to note that the ltc3646 will maintain output voltage regulation if these limits are exceeded, but the t on(min) limit may be reached resulting in the part switching at a frequency lower than the programmed switching frequency. choosing compensation components loop compensation is a complicated subject and applica- tion note 76 is recommended reading for a full discussion on maximizing loop bandwidth in a current mode switch- ing regulator. this section will provide a quick method on choosing proper components to compensate the ltc3646 regulators. figure 3 shows the recommended components to be con- nected to the ith pin, and figure 4 shows an approximate bode plot of the buck regulator loop using these compo- nents. it is assumed that the major poles in the system (the output capacitor pole and the error amplifier output pole) are located at a frequency lower than the crossover frequency. a pplica t ions i n f or m a t ion the first step is to choose the crossover frequency f c . higher crossover frequencies will result in a faster loop transient response; however, in order to avoid higher order loop dynamics from the switching power stage, it is recommended that f c not exceed one-tenth the switching frequency (f o ). once f c is chosen, the value of r comp that sets this cross- over frequency can be calculated by the following equation: r comp = 2 ? f c ? c out g m(ea) ? g m(mod) ? ? ? ? ? ? ? ? v out v fb ? ? ? ? ? ? where g m(ea) is the error amplifier transconductance (see the electrical characteristics section), and g m(mod) is the modulator transconductance ( the transfer function from ith voltage to current comparator threshold). for the ltc3646, this transconductance is nominally 1 C1 at room temperature. figure 3. compensation and filtering components figure 4. bode plot of regulator loop ltc3646 c byp r comp c comp 3634 f03 ith sgnd ? p log (?) ? c ? z 3646 f04 ?1 0db |h(s)| ?2
ltc3646/ltc3646-1 16 36461f once r comp is determined, c comp can be chosen to set the zero frequency (f z ): f z = 1 2 ? c comp ? r comp for maximum phase margin, f z should be chosen to be less than one-tenth of f c . since the ith node is sensitive to noise coupling, a small bypass capacitor (c byp ) may be used to filter out board noise. however, this cap contributes a pole at f p and may introduce some phase loss at the crossover frequency: f p = 1 2 ? c byp ? r comp for best results, f p should be set high enough such that phase margin is not significantly affected. if necessary, a capacitor c f ( as shown in figure 2) may be used to add some phase lead. though better load transient response can generally be achieved with external compensation, at switching fre- quencies above 1 mhz, component count can be reduced by connecting the ith pin to intv cc enabling internal compensation. when using internal compensation, a reasonable starting point for the minimum amount of output capacitance necessary for stability can be found as the greater of 15f or c out defined by the equation: c out > 3 ? 10 C5 /v out checking transient response the regulator loop response can be checked by observing the response of the system to a load step. when configured for external compensation, the availability of the ith pin not only allows optimization of the control loop behavior but also provides a dc- coupled and ac- filtered closed- loop response test point. the dc step, rise time, and settling behavior at this test point reflect the systems closed- loop response. assuming a predominantly second order system, the phase margin and/or damping factor can be estimated by observing the percentage of overshoot seen at this pin. use a high impedance, low capacitance probe (>50m?, <5 pf). the ith external components shown in figure 3 will provide an adequate starting point for most a pplica t ions i n f or m a t ion applications. the series r-c filter sets the pole-zero loop compensation. the values can be modified from their suggested values once the final pc layout is done, and the particular switching frequency, output capacitor type and value have been chosen. the output capacitors need to be selected because their various types and values determine the loop feedback factor gain and phase. an output cur- rent pulse of 20% to 100% of full load current with a rise time of 1 s to 10 s will produce output voltage and ith pin waveforms that will give a sense of the overall loop stability without breaking the feedback loop. when observing the response of v out to a load step, the initial output voltage step may not be within the bandwidth of the feedback loop. as a result, the standard second order overshoot/dc ratio cannot be used to estimate phase margin. the output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply performance . for a detailed explanation of optimizing the compensation components, including a review of control loop theory, refer to application note 76. as shown in figure 2 a feed- forward capacitor, c f , may be added across feedback resistor r1 to improve the high frequency response of the system. capacitor c f provides phase lead by creating a high frequency zero with r1. in some applications severe transients can be caused by switching in loads with large (>10 f) input capacitors. the discharged input capacitors are effectively put in parallel with c out , causing a rapid drop in v out . no regulator can deliver enough current to prevent this output droop if the switch connecting the load has low resistance and is driven quickly. the solution is to limit the turn-on speed of the load switch driver. a hot swap? controller is designed specifically for this purpose and usually incorporates cur- rent limit, short-circuit protection and soft-start functions. mode/sync operation the mode/sync pin is a multipurpose pin allowing both mode selection and operating frequency synchronization. connecting this pin to intv cc enables burst mode operation for superior efficiency at low load currents at the expense of slightly higher output voltage ripple. when the mode/ sync pin is pulled to ground, forced continuous mode
ltc3646/ltc3646-1 17 36461f operation is selected creating the lowest fixed output ripple at the expense of light load efficiency. the ltc3646 will detect the presence of the external clock signal on the mode/sync pin and synchronize the internal oscillator to the phase and frequency of the in- coming clock. the presence of an external clock will place the ltc3646 into forced continuous mode operation. for proper on-time, connect a resistor corresponding to the sync frequency between the rt pin and sgnd ( see the operating frequency section). the user should be aware that a clock with fast edges may drive this pin below the C0.3v rating of this pin and an r-c filter may be needed to prevent this condition. soft-start soft-start on the ltc3646 is implemented by internally ramping the reference signal fed to the error amplifier over approximately a 250 s period. figure 5 shows the behavior of the regulator during start-up. during the soft-start period, the inductor current is not allowed to reverse and discontinuous operation may occur under light load conditions. output power good the pgood output of the ltc3646 is driven by a 63 ( typical) open - drain pull- down device. this pin will become high impedance once the output voltage is within 5% (see v pgood thresholds) of the target regulation point allow- ing the voltage at pgood to rise via an external pull-up resistor (100 k typical). if the output voltage exits a 7.5% (see v pgood thresholds) regulation window around the target regulation point the open- drain output will pull down with 63 output resistance to ground, thus dropping the pgood pin voltage. a filter time of 30s ( typical at f o = 2.25 mhz) acts to prevent unwanted pgood output changes during v out transient events. this filter time varies as a function of programmed switching period. the output voltage must exit the 7.5% regulation window for approximately 70 switching cycles before the pgood pin pulls to ground (see figure 6). a pplica t ions i n f or m a t ion figure 6. pgood pin behavior pgood voltage v out ?7.5% ?5% 5% 7.5% 3646 f06 0% nominal output figure 5. start-up waveform i load = 50ma 100s/div 3646 f05 v out 5v/div i l 250ma/div run 5v/div
ltc3646/ltc3646-1 18 36461f efficiency considerations the percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. percent efficiency can be expressed as: % efficiency = 100% C (l1 + l2 + l3 +) where l1, l2, etc. are the individual loss terms as a per- centage of input power. although all dissipative elements in the circuit produce losses, three main sources account for the majority of the losses in the ltc3646 : 1) i 2 r loss , 2) switching losses and quiescent current loss , 3) transition losses and other system losses. 1. i 2 r loss is calculated from the dc resistance of the internal switches, r sw , and external inductor, r l . in continuous mode, the average output current will flow through inductor l but is chopped between the internal top and bottom power mosfets. thus, the series resis- tance looking into the sw pin is a function of both the top and bottom mosfets r ds(on) and the duty cycle (dc) as follows: r sw = (r ds(on)top )(dc) +(r ds(on)bot )(1 C dc) the r ds(on) for both the top and bottom mosfets can be obtained from the curves in the typical performance characteristics section. thus to obtain i 2 r loss: i 2 r loss = i out 2 ? (r sw + r l ) 2. the internal ldo supplies the power to the intv cc rail. the total power loss here is the sum of the switching losses and quiescent current losses from the control circuitry. each time a power mosfet gate is switched from low to high to low again, a packet of charge dq moves from v in to ground. the resulting dq/dt is a cur- rent out of intv cc that is typically much larger than the dc control bias current. in continuous mode , i gatechg = f o (q t + q b ), where q t and q b are the gate charges of the internal top and bottom power mosfets and f o is the switching frequency. for estimation purposes, (q t + q b ) on the ltc3646 is approximately 5nc. to calculate the total power loss from the ldo load, simply add the gate charge current and quiescent current and multiply by v in : p ldo = (i gatechg + i q ) ? svin as will be discussed below, in certain cases the overall efficiency can be improved by supplying the gate and quiescent current through the ext v cc pin. 3. other hidden losses such as transition loss, copper trace resistances, and internal load currents can account for additional efficiency degradations in the overall power system. transition loss arises from the brief amount of time the top power mosfet spends in the saturated region during switch node transitions. other losses, including diode conduction losses during dead time and inductor core losses, generally account for less than 2% total additional loss. transition loss can become significant at high v in or high switching frequencies. transition loss for the ltc3646 can be approximated by the following formula: loss (w atts) = i out ? v in 2 ? f o ? 10 C10 a pplica t ions i n f or m a t ion
ltc3646/ltc3646-1 19 36461f thermal considerations the ltc3646 requires the exposed package backplane metal ( pgnd) to be well soldered to the pc board to pro- vide good thermal contact. this gives the qfn and msop packages exceptional thermal properties, compared to other packages of similar size, making it difficult in normal operation to exceed the maximum junction temperature of the part. in many applications, the ltc3646 does not generate much heat due to its high efficiency. however, in applications in which the ltc3646 is running at a high ambient temperature, high input voltage, high switching frequency, and maximum output current, the heat dissi- pated may cause the part to exceed the maximum allowed junction temperature. if the junction temperature reaches approximately 175 c, both power switches will be turned off until temperature decreases approximately 10c. thermal analysis should always be performed by the user to ensure the ltc3646 does not exceed the maximum junction temperature. the temperature rise is given by: t rise = p d ja where p d is the power dissipated by the regulator and ja is the thermal resistance from the junction of the die to the ambient. consider the example in which an ltc3646ide-1 is operating with i out = 1.0 a, svin = 12 v, f = 3 mhz, v out = 1.8 v, and a board temperature of 85c. from the typical performance characteristics section, the r ds(on) of the top switch is found to be nominally 200m while that of the bottom switch is nominally 120m yielding an equivalent power mosfet resistance r sw of: r ds(on)top ? 1.8 12 + r ds(on)bot ? 10.2 12 = 132m from the previous section, i gatechg + i q is ~15 ma when f = 3 mhz. therefore, the total power dissipation due to resistive losses and ldo losses is: p d = i out 2 ? r sw + svin ? (i gatechg + i q ) p d = (1.0) 2 ? (0.132) + 12v ? 15ma = 312mw and the transition loss is: p t = 1.0 ? 12 2 ? 10 C10 ? 3.0 ? 10 6 = 43mw a pplica t ions i n f or m a t ion the dfn 4 mm 3mm package junction- to- ambient thermal resistance, ja , is approximately 43 c/w. therefore, the junction temperature of the regulator operating in a 85c ambient temperature is approximately: t j = (0.312 + 0.043) ? 43 + 85 = 100c which is below the specified maximum junction tempera- ture of 125c. high input voltage, high frequency applications may cause the internal ldo to generate significant heat. the intv cc current, which is dominated by the gate charge current, may be supplied by either the svin ldo or through the extv cc pin. when the voltage on the extv cc pin is less than 4.5v , the v in ldo is enabled. power dissipation for the ic in this case is highest and is equal to svin ? i intvcc . the gate charge current is dependent on operating frequency as discussed in the efficiency considerations section. for example, the ltc3646 intv cc current is approximately 15ma at 3 mhz operation . if v in is at the 40 v maximum, the loss in the on-chip ldo is: 40 v ? 0.015a = 0.60w in these situations it will be advantageous to bias the part through the extv cc pin if a suitable voltage source is available. when the voltage applied to extv cc rises above 4.5v (maximum 6.0 v), the svin ldo is turned off and an internal switch between the extv cc and intv cc pins is closed. this voltage is unregulated and so in this situation, intv cc = extv cc . using extv cc allows the control power to be derived from the output if the output voltage is between 4.5 v and 6.0v during normal operation and from the svin ldo when the output is out of regulation ( e.g., start-up, short-circuit). significant efficiency and thermal gains can be realized by powering intv cc from the output, since the power needed for the driver and control currents will be supplied from the buck converter instead of the internal linear regulator. for 4.5v to 6v regulator outputs, this means connecting the extv cc pin directly to v out . tying the extv cc pin to a 5.5v supply reduces the dissipated power in the previous example from 0.60w to approximately: 5.5 v ? 0.015a = 82.5mw
ltc3646/ltc3646-1 20 36461f the following list summarizes the three possible connec- tions for extv cc : 1. extv cc grounded. this will cause intv cc to be powered from the internal 5.0v regulator. 2. extv cc connected directly to v out . this is the normal connection for a 4.5 v to 6 v regulated output and pro- vides the highest efficiency. 3. extv cc connected to an external supply. if an external supply is available in the 4.5 v to 6 v range, it may be used to power extv cc . ensure that extv cc < v in . board layout considerations when laying out the printed circuit board, the following checklist should be used to ensure proper operation of the ltc3646. 1. does the capacitor c pvin connect to pvin and pgnd as close to the pins as possible? these capacitors provide the ac current to the internal power mosfets and drivers. the (C) plate of c pvin should be closely connected to pgnd and the (C) plate of c out . 2. the output capacitor, c out , and inductor l1 should be closely connected to minimize loss. the (C) plate of c out should be closely connected to pgnd and the (C) plate of c in . 3. the resistive divider, r1 and r2, must be connected between the (+) plate of c out and a ground line termi- nated near sgnd. the feedback signal, v fb , should be routed away from noisy components and traces such as the sw line, and its trace length should be minimized. in addition, rt and the loop compensation components should be terminated to sgnd. 4. keep sensitive components away from the sw pin. the r rt resistor, the feedback resistors, the compensation components, and the intv cc bypass capacitor should all be routed away from the sw trace and the inductor. 5. a ground plane is preferred, but if not available the signal and power grounds should be segregated with both connecting to a common, low noise reference point. the point at which the ground terminals of the v in and v out bypass capacitors are connected makes a good, low noise reference point. the connection to the pgnd pin should be made with a minimal resistance trace from the reference point. 6. flood all unused areas on all layers with copper in order to reduce the temperature rise of power components. these copper areas should be connected to the exposed backside connection of the ic. a pplica t ions i n f or m a t ion
ltc3646/ltc3646-1 21 36461f a pplica t ions i n f or m a t ion figure 7. example of power component layout for dfn package. because of the similar pinout, mse package layout is similar 3646 f07 pvin sw c pvin c out v out l1 c boost c vcc c svin r svin c comp r pgood r rt r comp c f r1 r2 gnd via to v out via to pvin via to intv cc via to gnd
ltc3646/ltc3646-1 22 36461f a pplica t ions i n f or m a t ion figure 8. board layout schematic pvin svin run intv cc pgood ith rt mode/sync extv cc boost sw v on v fb + ? switch control ltc3646 r pgood l1 sgnd pgnd c boost r1 c in 10f 0.6v r rt r comp r2 3646 f08 c out v out c f c vcc c comp pv in r svin c svin
ltc3646/ltc3646-1 23 36461f figure 9 a pplica t ions i n f or m a t ion design example as a design example, consider using the ltc3646-1 in an application with the following specifications: v in = 12v, v out = 1.8v, i out(max) = 1a, i out(min) = 10ma. because efficiency is important at both high and low load currents, burst mode operation and 1 mhz operation is chosen. first the correct r rt resistor value for 1 mhz switching frequency must be chosen. based on the equation dis- cussed previously, the closest standard resistor value for r rt is 90.9k. next, determine the inductor value for approximately 35% ripple current using: l = 1.8v 1mhz ? 350ma ? ? ? ? ? ? 1 ? 1.8v 12v ? ? ? ? ? ? = 4.37h a standard 4.7 h inductor would work well for this ap- plication. next c out is selected based on the required output transient performance and the required esr to satisfy the output voltage ripple. using a 15 f ceramic capacitor with an esr of 5m? will result in approximately 5mv of ripple. decoupling the pvin pin with a 22 f capacitor and the svin pin with a 1 f capacitor should be adequate for most applications. a 0.1 f boost capacitor should also work for most applications. to save board space the ith pin is connected to intv cc to select internal compensation . since the switching and q current drawn from the 12v supply is not a significant source of loss or heat, extv cc is disabled by tying the pin to sgnd. svin run intv cc mode/sync ith pgood rt extv cc pvin boost sw v on v fb ltc3646-1 l out 4.7h sgnd pgnd c boost 0.1f r1 150k c vcc 4.7f r pg 100k c svin 1f r2 75k 3646 f09 c f 1pf c out 15f v out 12v r rt 90.9k c pvin 22f
ltc3646/ltc3646-1 24 36461f typical a pplica t ions 12v to 1.8v output with 400khz external sync efficiency curve 50ma to 1a load step load current (a) 0.001 efficiency (%) 0.1 1 3646 ta02b 0 0.01 100 10 20 30 40 50 60 70 80 90 pvin svin run intv cc ith rt mode/sync extv cc boost sw v on v fb + ? switch control 400khz external clock ltc3646 0.1f l1 10h sgnd pgnd 22f 0.6v 226k 100k r comp 49.9k 3646 ta02a 4.7f c comp 220pf l1: wrth we-tpc-744-065-100 v in 12v 2 2.2f c f 4.7pf 274k 100f 137k v out 1.8v 40s/div 3646 ta02c v out 100mv/div ac-coupled i l 1a/div i load 1a/div
ltc3646/ltc3646-1 25 36461f typical a pplica t ions 24v input to 5v output at 1mhz frequency and extv cc efficiency curve 50ma to 1a load step pvin svin run intv cc pgood ith rt mode/sync extv cc boost sw v on v fb + ? switch control ltc3646 100k 2 l1 10h sgnd pgnd 0.1f 487k 22f 0.6v 90.9k r comp 100k 66.5k 3646 ta03a c out 30f v out 5v 20pf 4.7f c comp 33pf v in 24v 2.2f load current (a) 0.001 efficiency (%) 0.1 1 3646 ta03b 0 0.01 100 10 20 30 40 50 60 70 80 90 40s/div 3646 ta03c v out 200mv/div ac-coupled i l1 1a/div i load 1a/div
ltc3646/ltc3646-1 26 36461f p ackage descrip t ion de package 14-lead plastic dfn (4mm 3mm) (reference ltc dwg # 05-08-1708 rev b) 3.00 0.10 (2 sides) 4.00 0.10 (2 sides) note: 1. drawing proposed to be made variation of version (wged-3) in jedec package outline mo-229 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.40 0.10 bottom view?exposed pad 1.70 0.10 0.75 0.05 r = 0.115 typ r = 0.05 typ 3.00 ref 1.70 0.05 1 7 14 8 pin 1 top mark (see note 6) 0.200 ref 0.00 ? 0.05 (de14) dfn 0806 rev b pin 1 notch r = 0.20 or 0.35 45 chamfer 3.00 ref recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 2.20 0.05 0.70 0.05 3.60 0.05 package outline 0.25 0.05 0.25 0.05 0.50 bsc 3.30 0.05 3.30 0.10 0.50 bsc
ltc3646/ltc3646-1 27 36461f information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. p ackage descrip t ion mse package 16-lead plastic msop, exposed die pad (reference ltc dwg # 05-08-1667 rev e) msop (mse16) 0911 rev e 0.53 0.152 (.021 .006) seating plane 0.18 (.007) 1.10 (.043) max 0.17 ?0.27 (.007 ? .011) typ 0.86 (.034) ref 0.50 (.0197) bsc 16 16151413121110 1 2 3 4 5 6 7 8 9 9 1 8 note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 6. exposed pad dimension does include mold flash. mold flash on e-pad shall not exceed 0.254mm (.010") per side. 0.254 (.010) 0 ? 6 typ detail ?a? detail ?a? gauge plane 5.23 (.206) min 3.20 ? 3.45 (.126 ? .136) 0.889 0.127 (.035 .005) recommended solder pad layout 0.305 0.038 (.0120 .0015) typ 0.50 (.0197) bsc bottom view of exposed pad option 2.845 0.102 (.112 .004) 2.845 0.102 (.112 .004) 4.039 0.102 (.159 .004) (note 3) 1.651 0.102 (.065 .004) 1.651 0.102 (.065 .004) 0.1016 0.0508 (.004 .002) 3.00 0.102 (.118 .004) (note 4) 0.280 0.076 (.011 .003) ref 4.90 0.152 (.193 .006) detail ?b? detail ?b? corner tail is part of the leadframe feature. for reference only no measurement purpose 0.12 ref 0.35 ref mse package 16-lead plastic msop, exposed die pad (reference ltc dwg # 05-08-1667 rev e)
ltc3646/ltc3646-1 28 36461f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com ? linear technology corporation 2012 lt 1212 ? printed in usa r ela t e d p ar t s typical a pplica t ion part number description comments ltc3642 45v input capable with 60v transient protection, 50ma, synchronous micropower step-down dc/dc converter with i q = 12a v in(min) = 4.5v, v in(max) = 45v, 60v transient, v out(min) = 0.8v, i q = 12a, i sd < 1a, 3mm 3mm dfn-8, msop-8e packages ltc3631 45v input capable with 60v transient protection, 100ma, synchronous micropower step-down dc/dc converter with i q = 12a v in(min) = 4.5v, v in(max) = 45v, 60v transient, v out(min) = 0.8v, i q = 12a, i sd <1a, 3mm 3mm dfn-8, msop-8e packages ltc3632 50v input capable with 60v transient protection, 20ma, synchronous micropower step-down dc/dc converter with i q = 12a v in(min) = 4.5v, v in(max) = 45v, 60v transient, v out(min) = 0.8v, i q = 12a, i sd <1a, 3mm 3mm dfn-8, msop-8e packages ltc3601 15v, 1.5a (i out ), 4mhz, synchronous step-down dc/dc converter v in(min) = 4.5v, v in(max) = 15v, v out(min) = 0.6v, i q = 300a, i sd <1a, 4mm 4mm qfn-20, msop-16e packages ltc3603 15v, 2.5a (i out ), 3mhz, synchronous step-down dc/dc converter v in(min) = 4.5v, v in(max) = 15v, v out(min) = 0.6v, i q = 75a, i sd <1a, 4mm 4mm qfn-20, msop-16e packages lt3991 55v, 1.2a, 2.2mhz high efficiency micropower step-down dc/dc converter with i q = 2.8a v in(min) = 4.3v, v in(max) = 38v, v out(min) = 1.2v, i q = 2.8a, i sd <1a, 3mm 3mm dfn-10, msop-10e packages lt3682 36v, 60v max , 1a, 2.2mhz high efficiency micropower step-down dc/dc converter v in(min) = 3.6v, v in(max) = 36v, v out(min) = 0.8v, i q = 75a, i sd <1a, 3mm 3mm dfn-12 package lt3689 36v, 60v transient protection, 800ma, 2.2mhz high efficiency micropower step-down dc/dc converter with por reset and watchdog timer v in(min) = 3.6v, v in(max) = 36v, transient to 60v, v out(min) = 0.8v, i q = 75a, i sd <1a, 3mm 3mm qfn-16 package lt3480 36v with transient protection to 60v, 2a (i out ), 2.4mhz, high efficiency step-down dc/dc converter with burst mode operation v in(min) = 3.6v, v in(max) = 36v, transient to 60v, v out(min) = 0.78v, i q = 70a, i sd <1a, 3mm 3mm dfn-10, msop-10e packages lt3980 58v with transient protection to 80v, 2a (i out ), 2.4mhz, high efficiency step-down dc/dc converter with burst mode operation v in(min) = 3.6v, v in(max) = 58v, transient to 80v, v out(min) = 0.78v, i q = 85a, i sd <1a, 3mm 4mm dfn-16, msop-16e packages LT8610/ lt8611 42v, 2.5a, 96% efficiency, 2.2mhz synchronous micropower step-down dc/dc converter with i q = 2.5a v in = 3.4v to 42v, v out(min) = 0.97v, i q = 2.5a, i sd <1a, msop-16e package efficiency load current (a) 0.001 efficiency (%) 0.1 1 3646 ta04b 0 0.01 100 10 20 30 40 50 60 70 80 90 burst mode operation forced continuous pvin svin run intv cc pgood ith rt mode/sync extv cc boost sw v on v fb + ? switch control ltc3646 100k 2 l1 47h sgnd pgnd 0.1f 487k 22f 0.6v 180k r comp 402k 10.7k 3646 ta04a c out 33f v out 28v 4.7f c comp 220pf v in 40v 2.2f l1: wrth we-tpc-744-066-470 d1: dfls 1200

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